Home

Engineering

Publications

	DACS: Output Assign Module
	Output Assign Module The VHDL code used to synthesize the logic for the output assignment module decode GAL is shown below. ----------------------------------------------------------------------------- -- DACS : Distributed Audio Control System -- -- Copyright (C) 1997 Stephen Scott Richardson ----------------------------------------------------------------------------- -- File: outassn.vhd -- Date: 03.13.97 -- Target: Atmel ATF16V8B ----------------------------------------------------------------------------- -- Output assign board pbus address decoding GAL -- -- pbus addx function dir (from uC) -- ================================================== -- 0x14 led group 1 ena out -- 0x15 led group 2 ena out -- 0x16 7 segment ena out -- 0x30 button grp 1 nena in -- 0x31 button grp 2 nena in -- 0x32 button grp 3 nena in ----------------------------------------------------------------------------- ENTITY outassn_decode IS PORT ( addx_in : IN bit_vector (6 DOWNTO 0); nlatch_in : IN bit; nread_write_in : IN bit; btn_1_nena_out : OUT bit; btn_2_nena_out : OUT bit; btn_3_nena_out : OUT bit; seg7_ena_out : OUT bit; led_ena_2_out : OUT bit; led_ena_1_out : OUT bit; nsense_out : OUT bit ); -- Force a package and pinout ATTRIBUTE part_name of outassn_decode:entity is "C16V8"; ATTRIBUTE pin_numbers of outassn_decode:entity is "nread_write_in:1 nlatch_in:9 addx_in(0):2 addx_in(1):3 addx_in(2):4 addx_in(3):5 addx_in(4):6 addx_in(5):7 addx_in(6):8 nsense_out:12 btn_1_nena_out:13 btn_2_nena_out:14 btn_3_nena_out:15 seg7_ena_out:16 led_ena_2_out:17 led_ena_1_out:18"; END outassn_decode; ARCHITECTURE behavior OF outassn_decode IS BEGIN PROCESS (nlatch_in, addx_in, nread_write_in) BEGIN IF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0010100" THEN -- pbus 0x14 nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '1'; -- led 1 ena ACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0010101" THEN -- pbus 0x15 nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '1'; -- led 2 ena ACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0010110" THEN -- pbus 0x16 nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '1'; -- 7seg ena ACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '0' AND addx_in = "0110010" THEN -- pbus 0x32 (read) nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '0'; -- btn 3 nena ACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '0' AND addx_in = "0110001" THEN -- pbus 0x31 (read) nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '0'; -- btn 2 nena ACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '0' AND addx_in = "0110000" THEN -- pbus 0x30 (read) nsense_out <= '0'; -- pbus nsense ACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '0'; -- btn 1 nena ACTIVE ELSE -- not active nsense_out <= '1'; -- pbus nsense INACTIVE led_ena_1_out <= '0'; -- led 1 ena INACTIVE led_ena_2_out <= '0'; -- led 2 ena INACTIVE seg7_ena_out <= '0'; -- 7seg ena INACTIVE btn_3_nena_out <= '1'; -- btn 3 nena INACTIVE btn_2_nena_out <= '1'; -- btn 2 nena INACTIVE btn_1_nena_out <= '1'; -- btn 1 nena INACTIVE END IF; END PROCESS; END behavior; The pinout for the output assignment module decode GAL is shown below: C16V8A ___________________ nread_write_in =| 1| |20|* not used addx_in_0 =| 2| |19|* not used addx_in_1 =| 3| |18|= led_ena_1_out addx_in_2 =| 4| |17|= led_ena_2_out addx_in_3 =| 5| |16|= seg7_ena_out addx_in_4 =| 6| |15|= btn_3_nena_out addx_in_5 =| 7| |14|= btn_2_nena_out addx_in_6 =| 8| |13|= btn_1_nena_out nlatch_in =| 9| |12|= nsense_out not used *|10| |11|* not used ___________________	Table of Contents [Whole document in PDF 1.9MB] [more photos and information] Contents List of Figures List of Tables Executive Summary What Does the System do? Why Design and Implement this System? Project Goals Deliverables Conclusions Introduction Design Methodologies Application Analysis System Overview High-Level Hardware Specifications Control Board Mixer Unit Module-Level Hardware Specifications Control Board Mixer Unit Inter-Module Specifications Control Board Mixer Unit Digital Control Bus Hardware Schematics Control Board Mixer Unit Hardware Verification Control Board Mixer Unit Hardware PC Board Designs Control Board Mixer Unit Hardware Chassis Control Board Mixer Unit High-Level Firmware Design Control Board Mixer Unit The DACS Firmware Library Firmware Protocols Serial Communications Protocol Firmware Modules Firmware Library Control Board Mixer Unit Firmware Code Firmware Library, dacslib Control Board Mixer Unit High-Level Software Design Overall System: The Distributed Concept Functional Design Software Graphical User Interface Software Code MIDI Controller VHDL Code Control Board Mixer Unit Axiom MC68HC11 Single Board Computer References References Books Data Books and Data Sheets Web Sites About this document ...

Page last modified:

Copyright © 1993-2000 prefect - All Rights Reserved.