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This appendix includes the VHDL code used to synthesize the logic for the
GAL16V8 devices used as Pbus address decoders throughout the system.
It is important to note that individualized addresses were required for each
board in the systems.  This required essentially identical VHDL code
for duplicate boards, with the actual address changed.  In these
cases, only a representative piece of VHDL code is included.  It
should be clear to those familiar with VHDL how to change the actual
decoded addresses.  Each piece of code forces the pinouts, rather than
allowing the compiler to handle those decisions.  This was done
because the PC boards were designed in advance of the GALs, with an
assumed pinout.
All of the VHDL code is well commented, thus no additional description
is given with the code.  For each piece of VHDL code, the pin report
is included for reference.
The VHDL code was compiled into standard JEDEC files through the use
of the Cypress Warp VHDL Synthesizer, running on the author's Sun
SPARCstation IPC.  The Atmel GALs were programmed using a universal
programmer in the WPI ECE Shop.
  
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 Next: Control Board
 Up: mqp
 Previous: TCP/IP Server Library Code,
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Steve Richardson
2000-07-06
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